FIG. 1A is a schematic diagram illustrating a conventional display device. The display device 10 includes a control circuit 12 and a display panel 19, and the control circuit 12 includes a timing controller 13, a source module 15 and a gate module 17.
The timing controller 13 receives input video data from an image or graphic processing circuit, which changes the input video data to be compatible with the display panel 19. The input video data are stored in a frame buffer 131, and capacity of the frame buffer 131 may vary. The timing controller 13 controls operation and timing of the source module 15 through a data timing signal Sdt and data driving signals Srgb including RGB input information, and the timing controller 13 controls operation and timing of the gate module 17 through a gate timing signal Sgt.
The display panel 19 includes M data lines D(1)˜D(M) and N gate lines G(1)˜G(N) crossing each other and M×N pixel elements P(1,1)˜P(M,N). Pixel elements P(1,1)˜P(M,N) are arranged at intersections of data lines D(1)˜D(M) and gate lines G(1)˜G(N) to form an M×N pixel element array. It is noted that M and N are positive number, and the number of pixel elements and the arrangement of which are not restricted.
The source module 15 further includes a data driving circuit 151 and M source drivers SD(1)˜SD(M). The data driving circuit 151 is electrically connected to the timing controller 13 and source drivers SD(1)˜SD(M). The timing controller 13 aligns the RGB information in the input video signal in accordance with the display panel 19 and supplies the RGB information to the data driving circuit 15 through data driving signals Srgb. After receiving data driving signals Srgb and the data timing signal Sdt, the data driving circuit 151 generates data control signals Sdc and transmits the data control signals Sdc to source drivers SD(1)˜SD(M).
Source drivers SD(1)˜SD(M) are respectively electrically connected to pixel elements arranged at M columns through their corresponding data lines D(1)˜D(M). After receiving the data control signals Sdc from the data driving circuit 151, the source drivers SD(1)˜SD(M) transmit analog data voltages to pixel elements P(1,1)˜P(M,N), as data signals, through the data lines D(1)˜D(M). For example, source driver SD(1) is electrically connected to pixels elements P(1,1)˜P(1,N) arranged at the first column through data line D(1). Accordingly, the analog data voltage being generated by source driver SD(1) is transmitted to pixel elements P(1,1)˜P(1,N).
The gate module 17 further includes N gate drivers GD(1)˜GD(N) to respectively generate gate signals being transmitted through gate lines G(1)˜G(N). Gate drivers GD(1)˜GD(N) are respectively electrically connected to pixel elements at the same horizontal pixel line through their corresponding gate lines G(1)˜G(N). For example, gate driver GD(1) is electrically connected to pixels elements P(1,1)˜P(M,1) arranged at the first horizontal pixel line through gate line G(1).
Internal circuits of pixel elements P(1,1)˜P(M,N) are similar. At the lower right corner of FIG. 1, the dotted frame represents an internal circuit of pixel element P(M, N). Pixel element P(M,N) is arranged at the M-th column and the N-th horizontal pixel line. Pixel element P(M,N) includes a thin-film-transistor (hereinafter, TFT) MMN and a capacitor CA. Gate terminal of the TFT MMN is electrically connected to the N-th gate line G(N), source terminal of the TFT MMN is electrically connected to the M-th data line D(M), and the drain terminal of the TFT MMN is electrically connected to a terminal of the capacitor CMN. The other terminal of the capacitor CMN is electrically connected to a ground terminal (Gnd).
FIG. 1B is a schematic diagram illustrating frame display sequence of the conventional display device. Frame rate, also known as frame frequency, is the frequency (rate) at which the display device 10 displays consecutive frames 18 in one second (1 sec). As shown in FIG. 1B, fFrame indicates the frame rate. Typically, 60 frames or 120 frames are displayed in one second, that is, fFrame=60 or fFrame=120.
FIG. 1C is a schematic waveform diagram illustrating signals related to the conventional display device. Signals related to two consecutive frames, frame(k) and frame(k+1) are illustrated as example.
For displaying frame(k), the control circuit 12 generates signals related to frame(k) and transmits these signals to the display panel 19 in a frame duration Tframe between time point t1 and time point t5. For displaying frame(k+1), the control circuit 12 generates signals related to frame(k+1) and transmits these signals to the display panel 19. A frame duration Tframe corresponding to frame(k+1) is between time point t5 and time point t9. The frame duration Tframe is related to the frame rate “fFrame” of the display panel 19 as mentioned in FIG. 1B, that is, Tframe=1/fFrame.
Both the frame durations for displaying frame(k) and frame(k+1) are divided into N horizontal periods Thr, and each horizontal period Thr is corresponding to a horizontal pixel line. Therefore, the horizontal period Thr can be defined as Thr=Tframe/N. The horizontal period Thr is related to frame rate fFrame and resolution of the display device 10. The higher the frame rate fFrame of the display panel 19, the shorter the horizontal period Thr is. The higher the resolution of the display panel 19, the shorter the horizontal period Thr is. For the sake of illustration, the resolutions illustrated in the context focus on an active area (hereinafter, AA) within the display panel 19. Applications including non-AA are analogue and not redundantly illustrated.
When the display device 10 displays frames according to high definition (HD) standard, 1080 horizontal pixel lines of resolution is required to support 1920×1080 video format, and the frame duration Tframe is divided into 1080 horizontal periods Thr. When the display device 10 displays frames according to ultra-high-definition (UHD) standard, 2160 horizontal pixel lines of resolution is required to support 3840×2160 video format, and the frame duration Tframe is divided into 2160 horizontal periods Th.
Table 1 represents the horizontal period Thr based on different combination of the frame duration Tframe and the resolution of the display device 10.
TABLE 1frame ratehorizontal period(fFrame)resolution(Thr)601920 × 10801/(60 × 1080)3840 × 21601/(60 × 2160)1201920 × 10801/(120 × 1080)3840 × 21601/(120 × 2160)
Please refer to FIGS. 1A and 1C together. The gate module 17 receives the gate timing signal Sgt from the timing controller 13, and shifts the gate timing signal Sgt to generate gate pulses. These gate pulses are used as gate signals, and the gate signals are transmitted to the display plane through gate lines G(1)˜G(N).
Display of the k-th frame frame(k) is illustrated. Between time point t1 and time point t2, source drivers SD(1)˜SD(M) jointly transmit analog data voltages to pixel elements P(1,1)˜P(M,1) arranged at the first horizontal pixel line (h=1), and gate driver GD(1) transmits a gate pulse between time point t1 and time point t2. Between time point t2 and time point t3, source drivers SD(1)˜SD(M) jointly transmit analog data voltages to pixel elements P(1,2)˜P(M,2) arranged at the second horizontal pixel line (h=2), and gate driver GD(2) transmits another gate pulse. Similarly, between time point t4 and time point t5, source drivers SD(1)˜SD(M) jointly transmit analog data voltages to pixel elements P(1,N)˜P(M,N) arranged at the N-th horizontal pixel line (h=N), and gate driver GD(N) transmits still another gate pulse.
Pixel elements P(1,N)˜P(M,N) in FIG. 1A are utilized to display pixel data between time point t4 and time point t5, and between time point t8 and time point t9. The operation of pixel element P(M,N) is illustrated below as an example.
During time point t4 and time point t5, the TFT MMN is tuned on because its gate terminal receives the high level of the N-th gate line G(N), and the M-th data line D(M) transmits the analog data voltage to the source terminal of the TFT MMN. Therefore, the TFT MMN is turned on and the capacitor CMN is charged by the M-th data line D(M). Within the duration of displaying frame(k), the TFT MMN is turned on just between time point t4 and time point t5, and the TFT MMN is turned off between time point t1 and time point t4.
Similarly, during time point t8 and time point t9, the TFT MMN is turned on and the capacitor CMN is charged by the M-th data line D(M). Within the duration of displaying frame(k+1), the TFT MMN is turned on just between time point t8 and time point t9, and the TFT MMN is turned off between time point t5 and time point t8.
Based on the above illustrations, in N horizontal periods Thr of the frame duration Tframe, pixel elements P(1,N)˜P(M,N) arranged at N horizontal pixel lines are alternatively controlled to display pixel data, and the capacitors of pixel elements P(1,N)˜P(M,N) are alternatively charged.
With the increase of frame rate fFrame and resolution of the display device 10, the TFTs of pixel elements P(1,N)˜P(M,N) are switched more often and the capacitors of pixel elements P(1,N)˜P(M,N) are charged more often. In consequence, more power consumption is required to charge the capacitors of pixel elements P(1,N)˜P(M,N). The increase of power consumption brings heat to source drivers SD(1)˜SD(M), so that temperature of source drivers SD(1)˜SD(M) tend to be high. However, high temperature of source drivers SD(1)˜SD(N) may result in malfunction of the display device 10. Therefore, lowering temperature of source drivers SD(1)˜SD(N) becomes an important issue.